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document number: mma52xxakw rev. 0, 09/2012 freescale semiconductor data sheet: technical data ? 2012 freescale semiconductor, inc. all righ ts reserved. xtrinsic mma52xxakw psi5 inertial sensor the mma52xxakw family, a safeassure solution, includes the psi5 version 1.3 asynchronous mode compatible overdamped x-axis satellite accelerometers. features ? 60g to 480g full-scale range ? 400 hz, 3-pole low-pass filter ? single pole, high-pass filter with fast startup and output rate limiting ? psi5 version 1.3 asynchronous mode compatible ? psi5-a10p-228/1l compatible ? baud rate: 125 kbaud ? 10-bit data ? even parity error detection ? 16 s internal sample rate, with interpolation to 1 s ? pb-free 16-pin qfn, 6 by 6 package ? qualified aecq100, revision g, grade 1 (-40 c to +125 c) ( http://www.aecouncil.com/ ) typical applications ? airbag front and side crash detection ordering information device axis range package shipping MMA5206AKW x 60g 2086-01 tubes mma5212akw x 120g 2086-01 tubes mma5224akw x 240g 2086-01 tubes mma5248akw x 480g 2086-01 tubes MMA5206AKWr2 x 60g 2086-01 tape & reel mma5212akwr2 x 120g 2086-01 tape & reel mma5224akwr2 x 240g 2086-01 tape & reel mma5248akwr2 x 480g 2086-01 tape & reel 16-pin qfn case 2086-01 pin connections bottom view top view v cc v ss nc v ssa test v buf d out d in v rega cs v reg v ss i data slck v ssa nc 1 2 3 4 5 6 7 8 12 11 10 9 16 15 14 13 17 mma52xxakw
sensors 2 freescale semiconductor, inc. mma52xxakw application diagram figure 1. application diagram device orientation figure 2. device orientation diagram external component recommendations ref des type description purpose c1 ceramic 2.2 nf, 10%, 50v minimum, x7r v cc power supply decoupling and signal damping c3 ceramic 470 pf, 10%, 50v minimum, x7r i data filtering and signal damping c2 ceramic 15 nf, 10%, 50v minimum, x7r v cc power supply decoupling c4, c5, c6 ceramic 1 f, 10%, 10v minimum, x7r voltage regulator output capacitor(s) r1 general purpose 82, 5%, 200 ppm v cc filtering and signal damping r2 general purpose 27 , 5%, 200 ppm i data filtering and signal damping c1 c6 vv buf v ce v ss c4 c5 v reg v rega cs sclk do di mma51xx v ssa v ss v cc v buf r1 r2 i data c3 c2 note: pin names and references may differ from psi5 v1.3 pin names and references x: 0g earth ground x: +1g x: 0g x: -1g x: 0g x: 0g xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx
sensors freescale semiconductor, inc. 3 mma52xxakw internal block diagram figure 3. block diagram self-test interface ? converter v cc serial encoder v buf sync pulse detection programming interface v buf v ss buffer regulator voltage digital regulator voltage analog regulator voltage v reg v rega v rega v reg v cc v reg v rega v reg reference voltage v ref v ssa d in spi d out cs sclk i data v buf control logic otp array g-cell control in status out sinc filter compensation lpf iir dsp hpf low voltage detection offset monitor
sensors 4 freescale semiconductor, inc. mma52xxakw 1 pin connections figure 4. top view, 16-pin qfn package table 1. pin description pin pin name formal name definition 1 v cc supply this pin is connected to the psi5 power and data line through a resistor and supplies power to the device. an external capac- itor must be connected between this pin and v ss . reference figure 1 . 2 v ss digital gnd this pin is the power supply return node for the digital circuitry. 3 i data response current this pin is connected to the psi5 power and data line through a resistor and modulates the response current for psi5 com- munication. reference figure 1 . 4 v ss digital gnd this pin is the power supply return node for the digital circuitry. 5 nc not connected this pin must be left unconnected in the application. 6 sclk spi clock this input pin provides the serial clock to the spi port for test purposes. an internal pulldown device is connected to this pi n. this pin must be grounded or left unconnected in the application. 7 d out spi data out this pin functions as the serial data output from the spi port for test purposes. this pin must be left unconnected in the appl i- cation. 8 d in spi data in this pin functions as the serial data input to the spi port fo r test purposes. an internal pu lldown device is connected to this pin. this pin must be grounded or left unconnected in the application. 9 v reg digital supply this pin is connected to the power supply for the internal digital circuitry. an external capacitor must be connected between this pin and v ss . reference figure 1 . 10 cs chip select this input pin provides the chip select to the spi port for test purposes. an internal pullup device is connected to this pin.t his pin must be left unconnected in the application. 11 v rega analog supply this pin is connected to the power supply for the internal analog circuitry. an external capacitor must be connected between this pin and v ssa . reference figure 1 . 12 vssa analog gnd this pin is the power supply return node for the analog circuitry. 13 v buf power supply this pin is connected to a buffer regulator for the internal circuitry. the buffer regulator supplies both the analog (v rega ) and digital (v reg ) supplies to provide immunity from emc and supply dropouts on v cc . an external capacitor must be connected between this pin and v ss . reference figure 1 . 14 test test pin this pin is must be grounded or left unconnected in the application. 15 nc not connected this pin must be left unconnected in the application. 16 vssa analog gnd this pin is the power supply return node for the analog circuitry. 17 pad die attach pad this pin is the die attach flag, a nd is internally connected to vss. corner pads corner pads the corner pads are internally connected to v ss . v cc v ss nc v ssa test v buf d out d in v rega cs v reg v ss i data slck v ssa nc 1 2 3 4 5 6 7 8 12 11 10 9 16 15 14 13 17
sensors freescale semiconductor, inc. 5 mma52xxakw 2 electrical characteristics 2.1 maximum ratings maximum ratings are the extreme limits to which the dev ice can be exposed without permanently damaging it. 2.2 operating range v l (v cc - v ss ) v h , t l t a t h , t 25 k/min, unless otherwise specified. # rating symbol value unit 1 2 3 supply voltage (v cc , i data ) reverse current 160 ma, t 80 ms continuous transient (< 10 s) v cc_rev v cc_max v cc_trans -0.7 +20.0 +25.0 v v v (3) (3) (9) 4 v buf, test -0.3 to +4.2 v (3) 5 v reg , v rega , sclk, cs , d in , d out -0.3 to +3.0 v (3) 6 powered shock (six sides, 0.5 ms duration) g pms 2000 g (3) 7 unpowered shock (six sides, 0.5 ms duration) g shock 2500 g (3) 8 drop shock (to concrete, tile or steel surface, 10 drops, any orientation) h drop 1.2 m (5) 9 10 11 12 electrostatic discharge (per aecq100) external pins (v cc , i data , v ss , v ssa ), hbm (100 pf, 1.5 k ) hbm (100 pf, 1.5 k ) cdm (r = 0 ) mm (200 pf, 0 ) v esd v esd v esd v esd 4000 2000 1500 200 v v v v (5) (5) (5) (5) 13 14 temperature range storage junction t stg t j -40 to +125 -40 to +150 c c (3) (9) 15 thermal resistance jc 2.5 c/w (9, 14) # characteristic symbol min typ max units 16 17 supply voltage v cc v cc_uv v l 4.2 v vcc_uv_f ? ? v h 17.0 v l v v (1) (9) 18 19 operating temperature range t a t a t l -40 -40 ? ? t h +105 +125 c c (1) (3)
sensors 6 freescale semiconductor, inc. mma52xxakw 2.3 electrical characteristics - supply and i/o v l (v cc - v ss ) v h , t l t a t h , t 25 k/min, unless otherwise specified. # characteristic symbol min typ max units 20 quiescent supply current * i idle 4.0 ? 8.0 ma (1) 21 modulation supply current * i mod i idle + 22.0 i idle + 26.0 i idle + 30.0 ma (1) 22 inrush current (power on until v buf , v reg , v rega stable) i inrush ?? 3 0m a( 3 ) 23 24 25 internally regulated voltages v buf v reg v rega * * * v buf v reg v rega 3.60 2.425 2.425 3.80 2.50 2.50 4.00 2.575 2.575 v v v (1) (1) (1) 26 27 28 29 30 31 32 33 low voltage detection threshold v cc falling v buf falling v reg falling v rega falling hysteresis v cc v buf v reg v rega v vcc_uv_f v buf_uv_f v reg_uv_f v rega_uv_f v cc_hyst v buf_hyst v reg_hyst v rega_hyst 3.40 2.95 2.15 2.15 0.10 0.05 0.05 0.05 3.70 3.15 2.25 2.25 0.25 0.10 0.10 0.10 4.0 3.35 2.35 2.35 0.40 0.15 0.15 0.15 v v v v v v v v (3, 6) (3, 6) (3, 6) (3, 6) (3) (3) (3) (3) 34 35 external capacitor (v buf , v reg , v rega ) capacitance esr (including interconnect resistance) esr 500 0 1000 ? 1500 200 nf m (9) (9) 36 output high voltage (do) i load = 100 av oh v reg - 0.1 ? ? v (9) 37 output low voltage (do) i load = 100 av ol ??0 . 1v( 9 ) 38 input high voltage cs , sclk, di v ih 0.7 * v reg ??v( 9 ) 39 input low voltage cs , sclk, di v il ? ? 0.3 * v reg v(9) 40 41 input current high (at v ih ) (di) low (at v il ) (cs ) i ih i il -100 10 ? ? -10 100 a a (9) (9) 42 pulldown resistance (sclk) r pd 20 ? 100 k (9)
sensors freescale semiconductor, inc. 7 mma52xxakw 2.4 electrical characteristi cs - sensor and signal chain v l (v cc - v ss ) v h , t l t a t h , t 25 k/min, unless otherwise specified. # characteristic symbol min typ max units 43 44 45 46 47 48 49 50 51 52 sensitivity (10-bit output @ 100 hz, referenced to 0 hz) 60g range 120g range 240g range 480g range total sensitivity error (including non-linearity) t a = 25 c, 240g t l t a t h , 240g t l t a t h , 240g, v vcc_uv_f v cc v l t a = 25 c, > 240g t l t a t h , > 240g t l t a t h , > 240g, v vcc_uv_f v cc v l * * * * * * * * sens sens sens sens sens_240 sens_240 sens_240 sens_480 sens_480 sens_480 ? ? ? ? -5 -7 -7 -5 -7 -7 8 4 2 1 ? ? ? ? ? ? ? ? ? ? +5 +7 +7 +5 +7 +7 lsb/g lsb/g lsb/g lsb/g % % % % % % (1) (1) (1) (1) (1) (1) (9) (1) (1) (9) 53 54 digital offset before offset cancellation 10-bit 10-bit, t l t a t h , v vcc_uv_f v cc v l * off 10bit off 10bit -52 -52 0 0 +52 +52 lsb lsb (1) (9) 55 56 digital offset after offset cancellation 10-bit, 0.3 hz hpf or 0.1 hz hpf 10-bit, 0.04 hz hpf * * off 10bit off 10bit -1 -2 0 0 +1 +2 lsb lsb (1) (9) 57 continuous offset monitor limit 10-bit output, before compensation off mon -66 ? +66 lsb (3) 58 range of output (10-bit mode) acceleration range -480 ? +480 lsb (3) 59 60 cross-axis sensitivity z-axis to x-axis y-axis to x-axis * * v zx v yx -5 -5 ? ? +5 +5 % % (3) (3) 61 system output noise peak (10-bit mode, 1 hz - 1 khz, all ranges) * n peak -4 ? +4 lsb (3) 62 system output noise rms (10-bit mode, 1 hz - 1 khz, all ranges) * n rms ??+ 1 . 0l s b( 3 ) 63 64 non-linearity 10-bit output , 240g 10-bit output, > 240g nl out_240g nl out_480g -2 -2 ? ? +2 +2 % % (3) (3)
sensors 8 freescale semiconductor, inc. mma52xxakw 2.5 electrical characteristics - self-test and overload v l (v cc - v ss ) v h , t l t a t h , t 25 k/min, unless otherwise specified. # characteristic symbol min typ max units 65 66 67 68 10-bit output during active self-test (t l t a t h ) 60g range 120g range 240g range 480g range * * * * g st10_60x g st10_120x g st10_240x g st10_480x 120 40 56 8 ? ? ? ? 280 160 184 112 lsb lsb lsb lsb (3) (3) (3) (3) 69 acceleration (without hitting internal g-cell stops) 60g range positive/negative g g-cell_clip60x 400 456 500 g (9) 70 acceleration (without hitting internal g-cell stops) 120g range positive/negative g g-cell_clip120x 400 456 500 g (9) 71 acceleration (without hitting internal g-cell stops) 240g range positive/negative g g-cell_clip240x 1750 2065 2300 g (9) 72 acceleration (without hitting internal g-cell stops) 480g range positive/negative g g-cell_clip480x 1750 2065 2300 g (9) 73 ? and sinc filter clipping limit 60g range positive/negative g adc_clip60x 191 210 233 g (9) 74 ? and sinc filter clipping limit 120g range positive/negative g adc_clip120x 353 380 410 g (9) 75 ? and sinc filter clipping limit 240g range positive/negative g adc_clip240x 928 1055 1218 g (9) 76 ? and sinc filter clipping limit 480g range positive/negative g adc_clip480x 1690 1879 2106 g (9)
sensors freescale semiconductor, inc. 9 mma52xxakw 2.6 dynamic electrical characteristics - psi5 v l (v cc - v ss ) v h , t l t a t h , t 25 k/min, unless otherwise specified 2.7 dynamic electrical char acteristics - signal chain v l (v cc - v ss ) v h , t l t a t h , t 25 k/min, unless otherwise specified # characteristic symbol min typ max units 77 78 79 80 81 82 83 84 85 86 initialization timing phase 1 phase 2 (10-bit, asynchronous mode 0, k = 8) phase 3 (10-bit, asynchronous mode 0, st_rpt = 0) offset cancellation stage 1 operating time offset cancellation stage 2 operating time self-test stage 1 operating time self-test stage 2 operating time self-test stage 3 operating time self-test repetitions programming mode entry window t psi5_init1 t psi5_init2_10a0 t psi5_init3_10a0 t oc1 t oc2 t st1 t st2 t st3 st_rpt t pme ? ? ? ? ? ? ? ? 0 ? 532000 / f osc 512 * t async 19 * t async 320000 / f osc 280000 / f osc 128000 / f osc 128000 / f osc 128000 / f osc ? 300000 / f osc ? ? ? ? ? ? ? ? 5 ? s s s s s s s s s (7) (7) (7, 12) (7) (7) (7) (7) (7) (7, 12) (7) 87 data transmission single bit time (psi5 low bit rate) * t bit_low 7.6000 8.0000 8.4000 s(7) 88 modulation current (20% to 80% of i mod - i idle ) rise time t rise 324 463 602 ns (3) 89 position of bit transition (psi5 low baud rate) * t bittrans_lowbaud 49 50 51 % (7) 90 asynchronous response time * t async ? 912 / f osc ?s(7) # characteristic symbol min typ max units 91 internal oscillator frequency * f osc 3.80 4 4.20 mhz (1) 92 93 dsp low-pass filter (note15) cutoff frequency lpf0 (referenced to 0 hz) filter order lpf0 * * f c_lpf0 o lpf0 ? ? 400 3 ? ? hz 1 (7) (7) 94 95 96 97 98 99 100 101 102 103 104 105 dsp offset cancellation low-pass filter (note 15) offset cancellation low-pass filter input sample rate stage 1 cutoff frequency, startup phase 1 stage 1 filter order, startup phase 1 stage 2 cutoff frequency, startup phase 1 stage 2 filter order, startup phase 1 cutoff frequency, option 0 filter order, option 0 offset cancellation output update rate (10-bit mode) offset cancellation output step size (10-bit mode) offset monitor update frequency offset monitor count limit offset monitor counter size t oc_samplerate f c_oc10 o oc10 f c_oc03 o oc03 f c_oc0 o oc0 t offrate_10 off step_10 offmon osc offmon cntlimit offmon cntsize ? ? ? ? ? ? ? ? ? ? ? ? 256 10.0 1 0.300 1 0.100 1 f osc / 2e6 0.5 f osc /2000 4096 8192 ? ? ? ? ? ? ? ? ? ? ? ? s hz 1 hz 1 hz 1 s lsb hz 1 1 (7) (7) (7) (7) (7) (7) (7) (7) (7) (7) (7) (7) 106 107 108 109 sensing element natural frequency 60g 120g 240g 480g f gcell_x60 f gcell_x120 f gcell_x240 f gcell_x480 12651 12651 26000 26000 ? ? ? ? 13871 13871 28700 28700 hz hz hz hz (9) (9) (9) (9) 110 111 112 113 sensing element rolloff frequency (-3 db) 60g 120g 240g 480g f gcell_x60 f gcell_x120 f gcell_x240 f gcell_x480 938 938 3952 3952 ? ? ? ? 2592 2592 14370 14370 hz hz hz hz (9) (9) (9) (9) 114 115 116 117 sensing element damping ratio 60g 120g 240g 480g gcell_x60 gcell_x120 gcell_x240 gcell_x480 2.760 2.760 1.260 1.260 ? ? ? ? 6.770 6.770 3.602 3.602 ? ? ? ? (9) (9) (9) (9) 118 119 120 121 sensing element delay (@100 hz) 60g 120g 240g 480g f gcell_delay_x60 f gcell_delay_x120 f gcell_delay_x240 f gcell_delay_x480 63 63 13 13 ? ? ? ? 170 170 40 40 s s s s (9) (9) (9) (9) 122 package resonance frequency f package 100 ?? khz (9)
sensors 10 freescale semiconductor, inc. mma52xxakw 2.8 dynamic electrical char acteristics - supply and spi v l (v cc - v ss ) v h , t l t a t h , t 25 k/min, unless otherwise specified 1. parameters tested 100% at final test. 2. parameters tested 100% at wafer probe. 3. verified by characterization 4. * indicates critical characteristic. 5. verified by qualification testing. 6. parameters verified by pass/fail testing in production. 7. functionality guaranteed by modeling, simulation and/or desi gn verification. circuit integrity assured through iddq and scan testing. timing is determined by inter nal system clock frequency. 8. n/a. 9. verified by simulation. 10. n/a. 11. measured at v cc pin; v sync guaranteed across full v idle range. 12. self-test repeats on failure up to a st_rpt max times before transmitting sensor error message. 13. n/a. 14. thermal resistance between the die junction and the ex posed pad; cold plate is attached to the exposed pad. 15. filter cutoff frequencies are directly d ependent upon the internal oscillator frequency. # characteristic symbol min typ max units 123 quiescent current settling time (power applied to iq = i idle 2ma) t set ?? 5ms(3) 124 reset recovery internal delay (after internal por) t int_init ? 16000 / f osc ? s(7) 125 126 127 v cc micro-cut (c buf =c reg =c rega =1 f) survival time (v cc disconnect without reset, c buf =c reg =c rega =700 nf) survival time (v cc disconnect without reset, c buf =c reg =c rega =1 f) reset time (v cc disconnect above which reset is guaranteed) t vcc_microcutmin t vcc_microcut t vcc_reset 30 50 ? ? ? ? ? ? 1000 s s s (3) (3) (3) 128 129 v buf , capacitor monitor disconnect time ( figure 9 ) por to first capacitor test disconnect disconnect delay, asynchronous mode ( figure 9 ) t por_captest t captest_adly ? ? 12000 / f osc 688 / f osc ? ? s s (7) (7) 130 131 v reg , v rega capacitor monitor por to first capacitor test disconnect disconnect rate t por_captest t captest_rate ? ? 12000 / f osc 256 / f osc ? ? s s (7) (7) 132 133 134 135 136 137 138 139 140 141 142 143 144 145 serial interface timing (see figure 6 , c dout 80 pf, r dout 10 k ) clock (sclk) period (10% of v cc to 10% of v cc ) clock (sclk) high time (90% of v cc to 90% of v cc ) clock (sclk) low time (10% of v cc to 10% of v cc ) clock (sclk) rise time (10% of v cc to 90% of v cc ) clock (sclk) fall time (90% of v cc to 10% of v cc ) cs asserted to sclk high (cs = 10% of v cc to sclk = 10% of v cc ) cs asserted to d out valid (cs = 10% of v cc to d out = 10/90% of v cc ) data setup time (d in = 10/90% of v cc to sclk = 10% of v cc ) d in data hold time (sclk = 90% of v cc to d in = 10/90% of v cc ) d out data hold time (sclk = 90% of v cc to d out = 10/90% of v cc ) sclk low to data valid (sclk = 10% of v cc to d out = 10/90% of v cc ) sclk low to cs high (sclk = 10% of v cc to cs = 90% of v cc ) cs high to d out disable (cs = 90% of v cc to d out = hi z) cs high to cs low (cs = 90% of v cc to cs = 90% of v cc ) t sclk t sclkh t sclkl t sclkr t sclkf t lead t access t setup t hold_in t hold_out t valid t lag t disable t csn 320 120 120 ? ? 60 ? 20 10 0 ? 60 ? 1000 ? ? ? 15 15 ? ? ? ? ? ? ? ? ? ? ? ? 40 28 ? 60 ? ? ? 50 ? 60 ? ns ns ns ns ns ns ns ns ns ns ns ns ns ns (9) (9) (9) (9) (9) (9) (9) (9) (9) (9) (9) (9) (9) (9)
sensors freescale semiconductor, inc. 11 mma52xxakw figure 5. powerup timing figure 6. serial interface timing v cc por v cc_uv_f + v cc_hyst time v reg v buf v cc_uv_f v buf_uv_f + v buf_hyst v buf_uv_f v reg_uv_f + v reg_hyst v reg_uv_f v reg v rega_uv_f +v rega_hyst v rega_uv_f response terminated if in process t sclk sclk d in cs d out t sclkh t sclkl t access t sclkr t sclkf t lead t csn t setup t hold_in t valid t disable t hold_out t lag
sensors 12 freescale semiconductor, inc. mma52xxakw 3 functional description 3.1 user accessible data array a user accessible data array allows for each device to be cu stomized. the array consists of an otp factory programmable block, an otp user programmable block, and read-only regist ers for device status. the otp blocks incorporate independent error detection circuitry for fault detection (reference section 3.2 ). portions of the factory programmable array are reserved for factory-programmed trim values. th e user accessible data is shown in ta b l e 2 . type codes r: readable register via psi5 3.1.1 device serial number registers a unique serial number is programmed into the serial number re gisters of each device during manufacturing. the serial num- ber is composed of the following information: serial numbers begin at 1 for all produced devices in each lo t and are sequentially assigned. lot numbers begin at 1 and are sequentially assigned. no lot will contain more devices than ca n be uniquely identified by the 13-bit serial number. depending on lot size and quantities, all possible lot numbers and serial numbers may not be assigned. the serial number registers are included in the factory programmed otp crc verification. reference section 3.2 for details regarding the crc verification. beyond this, the contents of the seri al number registers have no impact on device operation or performance, and are only used for traceability purposes. table 2. user accessible data byte addr (xlong msg) register nibble addr (long msg) bit function nibble addr (long msg) bit function type 7654 3210 $00 sn0 $01 sn[7] sn[6] sn[5] sn[4] $00 sn[3] sn[2] sn[1] sn[0] r $01 sn1 $03 sn[15] sn[14] sn[13] sn[12] $02 sn[11] sn[10] sn[9] sn[8] $02 sn2 $05 sn[23] sn[22] sn[21] sn[20] $04 sn[19] sn[18] sn[17] sn[16] $03 sn3 $07 sn[31] sn[30] sn[29] sn[28] $06 sn[27] sn[26] sn[25] sn[24] $04 devcfg1 $ 0 90010 $08 0 rng[2] rng[1] rng[0] $05 devcfg2 $ 0 b0000 $ 0 a0000 $06 devcfg3 $ 0 d0000 $0c 0 0 0 0 $07 devcfg4 $ 0 f0000 $ 0 e0000 $08 devcfg5 $ 1 10000 $ 1 00000 $09 devcfg6 $ 1 30100 $ 1 20000 $0a devcfg7 $ 1 50000 $ 1 40000 $0b devcfg8 $ 1 71010 $ 1 60000 $0c sc $19 0 tm_b reserved iden_b $18 oc_init_b idef_b off_b 0 $0d mfg_id $ 1 b0000 $ 1 a0000 bit range content sn[12:0] serial number sn[31:13] lot number
sensors freescale semiconductor, inc. 13 mma52xxakw 3.1.2 factory configuration register (devcfg1) the factory configuration register is a factory programmed, read- only register which contains user specific device configuratio n information. the factory configuration register is in cluded in the factory programmed otp crc verification. 3.1.2.1 range indication bits (rng[2:0]) the range indication bits are factory programmed and indicate the full-scale range of the device as shown below. 3.1.3 status check register (sc) the status check register is a read-only register containing device status information. 3.1.3.1 test mode flag (tm_b) the test mode bit is cleared if the device is in test mode. 3.1.3.2 internal data error flag (iden_b) the internal data error bit is cleared if a register data error detection mismatch is detected in the user accessible otp array . a device reset is required to clear the error. location bit a d d r e s sr e g i s t e r76543210 $ 0 4d e v c f g 100100r n g [ 2 ]r n g [ 1 ]r n g [ 0 ] f a c t o r y d e f a u l t00100000 rng[2] rng[1] rng[0] full-scale acceleration range g-cell design psi5 init data transmission (d9) reference table 9 0 0 0 reserved n/a 0001 0 0 1 60g medium-g 0111 0 1 0 reserved n/a 0010 0 1 1 120 g medium-g 1000 1 0 0 reserved n/a 0011 1 0 1 240 g high-g 1001 1 1 0 reserved n/a 0100 1 1 1 480 g high-g 1010 location bit a d d r e s sr e g i s t e r76543210 $0c sc 0 tm_b reserved iden_b oc_init_b idef_b off_b 0 tm_b operating mode 0 test mode is active 1 test mode is not active iden_b error condition 0 error detection mismatch in user programmable otp array 1 no error detected
sensors 14 freescale semiconductor, inc. mma52xxakw 3.1.3.3 offset cancellation in it status flag (oc_init_b) the offset cancellation initialization status bit is set once the offset cancellation initialization process is complete, and t he filter has switched to normal mode. 3.1.3.4 internal factory data error flag (idef_b) the internal factory data error bit is cleared if a register data crc fault is detect ed in the factory programmable otp array. a device reset is require d to clear the error. 3.1.3.5 offset error flag (off_b) the offset error flag is cleared if the a cceleration signal reaches the offset limit. 3.2 otp array error detection the factory programmed otp array is verified for errors with a 3-bit crc. the crc verification is enabled only when the factory programmed array is locked. the crc verifica tion uses a generator polynomial of g(x) = x 3 + x + 1, with a seed value = ?111?. the crc is continuously calculated on the factory programmable array with the exceptio n of the factory lock bits. bits are fed in from right to left (lsb first), and top to bottom (lower addr esses first) in the register map. the calculated crc is then co mpared against the stored 3 bit crc. if a crc error is detected in the otp array, the idef_b bit is cleared in the sc register. the crc verification is completed on the memory registers which hold a copy of the fuse array values, not the fuse array val- ues. oc_init_b error condition 0 offset cancellation in initialization 1 offset cancellation initialization complete (t oc1 and t oc2 expired) idef_b error condition 0 crc error in factory programmable otp array 1 no error detected off_b error condition 0 offset error detected 1 no error detected
sensors freescale semiconductor, inc. 15 mma52xxakw 3.3 voltage regulators the device derives its internal supply voltage from the v cc and v ss pins. separate internal voltage regulators are used for the analog (v rega ) and digital circuitry (v reg ). the analog and digital regulators are supplied by a buffer regulator (v buf ) to provide immunity from emc and supply dropouts on v cc . external filter capacitors are required, as shown in figure 1 . the voltage regulator module includes voltage monitoring circuitry which holds the device in reset following power-on until the internal voltages have increased above the undervoltage detectio n thresholds. the voltage monitor asserts internal reset when the external supply or internally regulated voltages fall below the undervoltage detection thresholds. a reference generator pr o- vides a reference voltage for the ? converter. figure 7. voltage regulation and monitoring v rega v reg v cc voltage regulator reference generator v rega = 2.50 v digital logic dsp otp array oscillator ? converter bias generator trim trim v ref v ref_mod = 1.250 v v reg = 2.50 v voltage regulator v buf bandgap reference v buf v buf v ref v rega v ref por v cc comparator v ref comparator comparator v buf comparator v rega v reg voltage regulator micro-cut trim trim
sensors 16 freescale semiconductor, inc. mma52xxakw 3.3.1 v buf , v reg , and v rega regulator capacitor the internal regulators require an external capacitor between each of the regulator pins (v buf , v reg , or v rega ) and the as- sociated the v ss / v ssa pin for stability. figure 1 shows the recommended types and values for each of these capacitors. 3.3.2 v cc , v buf , v reg , and v rega undervoltage monitor a circuit is incorporated to monitor the supply voltage (v cc ) and all internally regulated voltages (v buf , v reg , and v rega ). if any of internal regulator voltages fall below the specified undervoltage thresholds in section 2 , the device will be reset. if v cc falls below the specified threshold, psi5 transmissions are te rminated for the present response. once the supply returns above the threshold, the device will respond to the next detected sync pulse. reference figure 8 . figure 8. v cc micro-cut response v cc por v reg time v buf v rega v cc undervoltage detected response terminated i data v cc micro-cut occurs
sensors freescale semiconductor, inc. 17 mma52xxakw 3.3.3 v buf , v reg , and v rega capacitance monitor a monitor circuit is incorporated to ensure predicta ble operation if the connection to the external v buf , v reg , or v rega , ca- pacitor becomes open. the v buf regulator is disabled t captest_adly seconds after each data transmission for a duration of t captest_time seconds. if the external capacitor is not present, the regulator voltag e will fall below the internal reset threshold, forcing a device reset. the v reg and v rega regulators are disabled at a continuous rate (t captest_rate ), for a duration of t captest_time seconds. if either external capacitor is not present, the associated regul ator voltage will fall below the internal reset threshold, for cing a device reset. figure 9. v buf capacitor monitor - asynchronous mode figure 10. v reg capacitor monitor cap_test v buf time capacitor present v buf_uv_f por capacitor open t captest_time i data t captest_adly cap_test v reg time capacitor present por capacitor open t captest_time t captest_rate v porvreg_f
sensors 18 freescale semiconductor, inc. mma52xxakw figure 11. v rega capacitor monitor 3.4 internal oscillator a factory trimmed oscillator is included as specified in section 2 . 3.5 acceleration signal path 3.5.1 transducer the transducer is an overdamped mass-spring-damper sy stem defined by the following transfer function: where: = damping ratio n = natural frequency = 2 ? ? f n reference section 2.7 for transducer parameters. 3.5.2 ? converter a sigma delta modulator converts the differential capacitance of th e transducer to a 1 mhz data str eam that is input to the dsp block. figure 12. ? converter block diagram cap_test v rega time capacitor present v porrega_f por capacitor open t captest_time t captest_rate hs () n 2 s 2 2 n s ?? ? n 2 ++ --------------------------------------------------------- = 1-bit quantizer z -1 1 - z -1 z -1 1 - z -1 first integrator second integrator 1 = 1 2 2 v x c int1 g-cell c bot c top c = c top - c bot ? _out v = 2 v ref adc dac v = c x v x / c int1
sensors freescale semiconductor, inc. 19 mma52xxakw 3.5.3 digital signal processing block a digital signal processing (dsp) block is used to perform sign al filtering and compensation. a diagram illustrating the signal processing flow within the dsp block is shown in figure 13 . figure 13. signal chain diagram 3.5.3.1 decimation sinc filter the serial data stream produced by the ? converter is decimated and converted to parallel values by a 3rd order 16:1 sinc filter with a decimation factor of 16. table 3. signal chain characteristics description sample time ( s) data width (bits) over range (bits signal width (bits) signal noise (bits) signal margin (bits) typical block latency reference a sd 1 1 1 203/f osc section 3.5.2 b sinc filter 16 20 13 section 3.5.3.2 c low-pass filter 16 26 4 10 3 9 reference section 3.5.3.2 section 3.5.3.2 d compensation 16 26 4 10 3 9 68/f osc e down sampling 16 26 4 10 3 9 f high-pass filter 16 26 4 10 3 9 reference section 3.5.3.3 section 3.5.3.3 g dsp sampling 16 10 4/f osc section 3.5.3.5 10-bit output scaling h interpolation 1 10 64/f osc section 3.5.3.5 ? _out sinc filter low-pass filter output output compensation a b c d interpolation scaling f offset rate limiting offset cancellation downsampling low-pass filter e cancellation output g h hz () 1z 16 ? ? 16 1 z 1 ? ? () ------------------------------------ - 3 =
sensors 20 freescale semiconductor, inc. mma52xxakw figure 14. sinc filter response, t s = 16 s
sensors freescale semiconductor, inc. 21 mma52xxakw 3.5.3.2 low-pass filter data from the sinc filter is processed by an infinite impulse response (iir) low-pass filter. note: low-pass filter values do not include g-cell frequency response. hz () a 0 n 11 z 0 ? () n 12 z 1 ? ? () n 13 z 2 ? ? () ++ d 11 z 0 ? () d 12 z 1 ? ? () d 13 z 2 ? ? () ++ ------------------------------------------------------------------------------------------------- n 21 z 0 ? () n 22 z 1 ? ? () n 23 z 2 ? ? () ++ d 11 z 0 ? () d 22 z 1 ? ? () d 23 z 2 ? ? () ++ ------------------------------------------------------------------------------------------------- ?? = table 4. low-pass filter coefficients description filter coefficients group delay 400 hz, 3-pole lpf a 0 5.189235225042199e-02 2816/f osc n 11 1.629077582099646e-03 d 11 1.0 n 12 1.630351547919014e-03 d 12 -9.481076477495780e-01 n 13 0d 13 0 n 21 2.500977520825902e-01 d 21 1.0 n 22 4.999999235890745e-01 d 22 -1.915847097557409e+00 n 23 2.499023243303036e-01 d 23 9.191065266874253e-01
sensors 22 freescale semiconductor, inc. mma52xxakw figure 15. low-pass filter characteristics: f c = 400 hz, 3-pole, t s = 16 s
sensors freescale semiconductor, inc. 23 mma52xxakw 3.5.3.3 offset cancellation the device provides an offset cancellation circuit to remove internal of fset error. a block diagram of the offset cancellation is shown in figure 16 . figure 16. offset cancellation block diagram the transfer function for the offset lpf is: response parameters are specified in section 2 and the offset lpf coefficients are specified in table 6 . during startup, two phases of the offset lpf are used to allow fo r fast convergence of the internal offset error during initial iza- tion. the timing and characteristics of each phase are shown in table 5 and table 6 and specified in section 2 . for more infor- mation regarding the startup timing, referenc e the psi5 initialization information in section 4.4 . the offset low-pass filter used in normal operation is selected by the oc_filt bit as shown in table 5 . during the initialization self-test phase, the offs et cancellation circuit output value is frozen. during normal operation, output rate limiting is applied to the output of the high-pass filter. rate limiting updates the offse t can- cellation output by off step_xx lsb every t offrate_xx seconds. to_output scaling offset cancellation a 0 n 1 n 2 z 1? ? () + d 1 d 2 z 1? ? () + ------------------------------------ - ? low-pass filter input data inc/dec counter clk out 0.5 hz (derived from f osc ) offmon neg offmon pos off_err inc/dec counter clk out up/down 2 khz (derived from f osc ) offmon cntlimit input data downsampled to 256 s hz () ao 0 no 1 no 2 z 1 ? ? () + do 1 do 2 z 1 ? ? () + ---------------------------------------------- ? = table 5. offset cancellation st artup characteristics and timing offset cancellation startup phase offset lpf output rate limiting total time for phase 1 10 hz bypassed 80 ms 2 0.3 hz bypassed 70 ms self-test 0.3 hz bypassed (frozen during st2) 96 ms per self-test sequence (up to 6 repeats) complete 0.1 hz enabled n/a
sensors 24 freescale semiconductor, inc. mma52xxakw figure 17. 10 hz offset cancellati on low-pass filter characteristics figure 18. 0.1 hz offset cancellation low-pass filter characteristics table 6. high-pass filter coefficients description coefficients group delay 10 hz hpf ao 0 0.015956938266754 16.384 ms no 1 0.499998132328277 do 1 1.0 no 2 0.499998132328277 do 2 -0.984043061733246 0.3 hz hpf ao 0 0.000482380390167 537.6 ms no 1 0.499938218213271 do 1 1.0 no 2 0.499938218213271 do 2 -0.999517619609833 0.1 hz hpf ao 0 0.0001608133316040 1591ms no 1 0.4999999403953552 do 1 1.0 no 2 0.4999999403953552 do 2 -0.9998391270637512
sensors freescale semiconductor, inc. 25 mma52xxakw 3.5.3.4 offset monitor the device includes an offset monitor circuit. the output of the single pole low-pass filter in the offset cancellation block i s continuously monitored against the offset limits specified in section 2.4 . an up/down counter is employed to count up if the output exceeds the limits, and to count down if th e output is within the limits. the output of the counter is compared against the cou nt limit offmon cntlimit . if the counter exceeds the limit, the off_b flag in the sc register is cleared. the counter rails once the max counter value is reached (offmon cntsize ). the offset monitor is disabled durin g initialization phase 1, phase 2, and phase 3. 3.5.3.5 data interpolation the device includes 16 to 1 linear data interpolation to minimize the system sample jitter. each result produced by the digital signal processing chain is delayed one sample time. 3.5.3.6 output scaling the 26-bit digital output from the dsp is clipped and scaled to a 10-bit word which spans the acceleration range of the device. figure 19 shows the method used to establ ish the output acceleration data wo rd from the 26-bit dsp output. figure 19. 10-bit output scaling diagram over range signal noise margin d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 ... d2 d1 d0 10-bit data word d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 using rounding
sensors 26 freescale semiconductor, inc. mma52xxakw 3.6 overload response 3.6.1 overload performance the device is designed to operate within a specified range. acce leration beyond that range (overload) impacts the output of the sensor. acceleration beyond the range of the device can gener ate a dc shift at the output of the device that is dependent upon the overload frequency and amplitude. the g-cell is overdamped, providing the optimal design for overload performance. however, the performance of the device during an overload c ondition is affected by many other parameters, including: ? g-cell damping ? non-linearity ? clipping limits ? symmetry figure 20 shows the g-cell, adc and output clippi ng of the device over frequency. the relevant parameters are specified in section 2 . figure 20. output clipping vs. frequency 3.6.2 sigma delta modulator over range response over range conditions exist when the signal level is beyond t he full-scale range of the device but within the computational limits of the dsp. the ? converter can saturate at levels above those specified in section 2 (g adc_clip ). the dsp operates predictably under all cases of over range, although the signal may include residual high frequency components for some time after returning to the normal range of operation due to non-linear effects of the sensor. 5khz f g-cell f lpf g adc_clip g g-cell_clip determined by g-cell 10khz g-cell rolloff acceleration (g) frequency (khz) lpf rolloff r e g i o n c l i p p e d b y g - c e l l r e g i o n c l i p p e d b y a d c r e g i o n o f s i g n a l d i s to r ti o n d u e to a s y m m e tr y a n d n o n - l i n e a r i ty region of no signal distortion beyond specification region of interest roll-off and adc clipping g range_norm determined by g-cell roll-off and full-scale range region clipped by output
sensors freescale semiconductor, inc. 27 mma52xxakw 4 psi5 layer and protocol 4.1 communication interface overview the communication interface between a master device and the mma52xx is established via a psi5 compatible 2-wire inter- face. figure 21 shows the psi5 master to slave connections. figure 21. psi5 satellite interface diagram 4.2 data transmission physical layer the device uses a two wire interface for both its power supply (v cc ), and data transmission. data transmissions from the de- vice to the psi5 master are accomplished via mo dulation of the current on the power supply line. 4.3 data transmission data link layer 4.3.1 bit encoding the device outputs data by modulation of the v cc current using manchester 2 encoding. data is stored in a transition occurring in the middle of the bit time. the signal idles at the normal quiescent supply current. a logic low is defined as an increase i n current at the middle of a bit time. a logic high is defined as a decrease in current at the middle of a bit time. there is alw ays a transition in the middle of the bit time. if consecutive ?1? or ?0? data are transmit ted, there will also be a transition at th e start of a bit time. figure 22. manchester 2 data bit encoding mma51xx v cc i data satellite module #1 v cc v ss master device discrete components v ss i mod current ?0? bit consecutive ?0? data bits idle current ?1? bit sensed high t bit sensed low consecutive ?1? data bits
sensors 28 freescale semiconductor, inc. mma52xxakw 4.3.2 data transmission transmission frames are composed of two start bits, a 10-bit data word, and error detection bit(s). data words are transmitted least-significant bit (lsb) first. a typical manche ster-encoded transmission frame is illustrated in figure 23 . figure 23. example manchester encoded data transfer - psi5-x10p 4.3.3 error detection error detection of the transmitted data is accomplished via a parity bit. even parity is employed. the number of logic ?1? bits in the transmitted message must be an even number. sb1 sb0 d0 d1 d2 d3 d4 d5 d8 d9 par ?0? ?0? ?1? ?1? ?1? ?0? ?0? ?1? ?1? ?0? ?1? data bit bit value d6 d7 ?1? ?1? t frame t bit t tran = t bit * 13 i mod sb1
sensors freescale semiconductor, inc. 29 mma52xxakw 4.3.4 data range values ta b l e 8 shows the details for each data range. table 7. psi5 data values 10-bit data value description decimal hex +511 $1ff reserved ? ? ? ? ? ? +502 $1f6 +501 $1f5 +500 $1f4 sensor defect error message +499 $1f3 reserved ? ? ? ? ? ? +489 $1e9 +488 $1e8 sensor busy +487 $1e7 sensor ready +486 $1e6 sensor ready, but unlocked +485 $1e5 reserved ? ? ? ? ? ? +481 $1e1 +480 $1e0 maximum positive acceleration value ? ? ? ? ? ? positive acceleration values +3 $03 +2 $02 +1 $01 0 0 0g level -1 $3ff negative acceleration values -2 $3fe -3 $3fd ? ? ? ? ? ? -480 $220 maximum negative acceleration value -481 $21f initialization data codes 10-bit status data nibble 1 - 16 (0000 - 1111) (dx) ? ? ? ? -496 $210 -497 $20f initialization data ids block id 1 - 16 (10-bit mode) (idx) ? ? ? ? -512 $200
sensors 30 freescale semiconductor, inc. mma52xxakw 4.4 initialization following powerup, the device proceeds through an initialization process which is divided into 3 phases: ? initialization phase 1: no data transmissions occur ? initialization phase 2: sensor self-test and transmission of configuration information ? initialization phase 3: transmi ssion of ?sensor busy?, and ?sensor ready? / ?sensor defect? message once initialization is completed the device begins normal mode operation, which continues as long as the supply voltage re- mains within the specified limits. figure 24. psi5 sensor 10-bit initialization during psi5 initialization, the device completes an intern al initialization process consisting of the following: ? power-on reset ? device initialization ? program mode entry verification ? offset cancellation initialization (2 stages) ?self-test figure 25 shows the timing for internal and external initialization. figure 25. initialization timing init 1 init 3 normal mode init 2 por i idle i idle + i mod t int_init t psi5_init1 self-test raw offset calculation psi5 initialization phase 1 t psi5_init2 t psi5_init3 psi5 initialization phase 2 psi5 initialization phase 3 psi5 normal mode por internal delay t oc1 offset cancellation stage 1 t st1 self-test deflection verification t st2 self-test normal data calculation t st3 st_rpt * t st self-test repeat (if necessary) t oc2 offset cancellation stage 2
sensors freescale semiconductor, inc. 31 mma52xxakw 4.4.1 psi5 initialization phase 1 during psi5 initialization p hase 1, the device begins internal initialization and self checks, but transmits no data. initializ ation begins with the sequence below and shown in figure 25 : ? internal delay to ensure analog circuitry has stabilized (t int_init ) ? offset cancellation phase 1 initialization (t oc1 ) ? offset cancellation phase 2 initialization (t oc2 ) 4.4.2 psi5 initialization phase 2 during psi5 initialization phase 2, the device continues it s internal self checks and transm its the psi5 initialization phase 2 data. initialization is transmitted using the initialization data codes and ids specified in table 9 , and in the order shown in figure 26 . figure 26. psi5 initialization phase 2 data transmission order (10-bit mode) the initialization phase 2 time is calculated with the following equation: where: ? trans nibble = # of transmissions per data nibble 2 for 10-bit data: 1 for id, and 1 for data ? k = the repetition rate for the data fields ? data fields = 32 data fields for 10-bit data ?t s-s = sync pulse period d1 d2 ... d32 id1 1 d1 1 id1 2 d1 2 ... id1 k d1 k id2 1 d2 1 id2 2 d2 2 ... id2 k d2 k ... id32 1 d32 1 id32 2 d32 2 ... id32 k d32 k repeat k times repeat k times ... repeat k times t phase2 trans nibble k datafields () t async =
sensors 32 freescale semiconductor, inc. mma52xxakw 4.4.2.1 psi5 initialization phase 2 in psi5 initialization phase 2, 10-bit mode, the device transmits a sequence of sensor specific configuration and serial number information. the transmission data is in conformance with the psi 5 specification, revision 1.3, revision 1.10. the data content and transmission format is shown in table 8 and table 9 . times are calculated using the equation in section 4.4.2 . table 8. initialization phase 2 time operating mode repetition rate (k) # of transmissions nominal phase 2 time asynchronous mode (228 s) 8 512 116.7 ms table 9. psi5 initialization phase 2 data psi5 v1.2 field id # psi5 v1.2 nibble id # page address psi5 nibble address register address description value f1 d1 0 0000 hard-coded protocol revision = v1.3 0100 f2 d2, d3 0001, 0010 hard-coded number of data blocks = 32 0010 0000 f3 d4, d5 0100, 0110 mfg_id[7:0] manufacturer id 0100 0110 f4 d6, d7 0101, 0110 hard-coded sensor type = acceleration (high-g) 0000 0001 f5 d8 0111 factory programmed axis 0000 d9 1000 60g: 0111 120g: 1000 240g: 1001 480g: 1010 range varies f6 d10 1001 devcfg2[7:4] sensor specific information 0000 d11 1010 devcfg2[3:0] sensor specific information 0000 f7 d12 1011 hard-coded product revision factory d13 1100 hard-coded product revision factory d14 1101 devcfg6[3:0] product revision 0000 f8 d15 1110 factory programmed 0001 d16 1111 0010 d17 1 0000 0000 d18 0001 0000 f9 d19 0010 sn0 (high nibble) mma52xx serial number factory d20 0011 sn0 (low nibble) mma52xx serial number factory d21 0100 sn1 (high nibble) mma52xx serial number factory d22 0101 sn1 (low nibble) mma52xx serial number factory d23 0110 sn2 (high nibble) mma52xx serial number factory d24 0111 sn2 (low nibble) mma52xx serial number factory d25 1000 sn3 (high nibble) mma52xx serial number factory d26 1001 sn3 (low nibble) mma52xx serial number factory d27 1010 factory programmed 0000 d28 1011 0000 d29 1100 0000 d30 1101 0000 d31 1110 0000 d32 1111 0000
sensors freescale semiconductor, inc. 33 mma52xxakw 4.4.3 internal self-test during psi5 initialization phase 2 and phase 3, the device comp letes it?s internal self-test as described below and shown in figure 25 . ? self-test phase 1 - raw offset calculation ? the average offset is calculated for t st1 (self-test disabled). ? self-test phase 2 - self-test deflection verification ? the offset cancellation value is frozen for t st2 + 2ms ? self-test is enabled ?after t st2 /2, the acceleration output value is averaged for t st2 /2 to determine the self-test value ? the self-test value is compared against the limits specified in section 2.5 ? self-test is disabled ? self-test phase 3 - self-test normal data calculation ? the average offset is calculated for t st3 ? if self-test passed, the device advances to normal mode ? if self-test failed, the device repeats self-t est phases 1 through 3 up to st_rpt times. 4.4.4 initialization phase 3 during psi5 initialization phase 3, the device completes it?s in ternal self checks, and transmit s a combination of ?sensor busy ?, ?sensor ready?, or ?sensor de fect? messages as defined in ta b l e 7 . self-test is repeated on failure up to st_rpt times to pro- vide immunity to misuse inputs during initialization. self-tes t terminates successfully after o ne successful self-test sequence . ta b l e 1 0 shows the nominal initialization phase 3 times for self-test repeats. times are calculated using the following equation. 4.5 error handling 4.5.1 sensor defect message the following failures will cause the device to transmit a ?sensor defect? error message: 4.5.2 no response error the following failures will cause the device to stop transmitting: table 10. initialization phase 3 time operating mode self-test repetitions # of sensor busy messages # of sensor ready or sensor defect messages nominal phase 3 time (ms) 10-bit asynchronous mode 0 (228 s) 02 2 0.91 1 423 96.90 2 844 192.89 3 1265 288.88 4 1686 384.86 5 2107 480.85 error condition error type offset error temporary (normal transmissions continue once o ffset returns within limits) self-test failure latched until reset iden_b, idef_b flag cleared latched until reset error condition error type undervoltage failure (v cc ) temporary: normal transmi ssions continue once voltage returns above failure limit) t psi5init3 roundup t intinit t oc1 t oc2 t st1 t st2 t st3 ++ () strpt 1 + () +++ () t psi5init1 t psi5init2xx + () ? t async --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 2 + ? ? ? ? t async =
sensors 34 freescale semiconductor, inc. mma52xxakw 5 package 5.1 case outline drawing reference freescale case outline drawing # 98asa00090d http://www.freescale.com/files/shared /doc/package_info/98asa00090d.pdf 5.2 recommended footprint reference freescale application note an3111, latest revision: http://www.freescale.com/files /sensors/doc/app _note/an3111.pd f table 11. revision history revision number revision date description of changes 0 09/2012 ? initial release.
document number: mma52xxakw rev. 0 09/2012 information in this document is provided solely to enable system and software implementers to use freescale products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. freescale reserves the right to make changes without further notice to any products herein. freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does freescale assume any liability arising out of the app lication or use of an y product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale data sheets and/or specifications can and do vary in differen t applications, and actual performance may vary over time. all operating parameters, including ?typicals,? must be validated for each customer application by customer?s technica l experts. freescale does not convey any license under its patent rights nor the rights of others. freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.reg.net/v2/webservices/fr eescale/docs/termsandconditions.htm. how to reach us: home page: freescale.com web support: freescale.com/support freescale, the freescale logo, altivec, c-5, codetest, codewarrior, coldfire, c-ware, energy efficient solutions logo, kinetis, mobilegt, powerquicc, processor expert, qoriq, qorivva, starcore, symphony, and vortiqa are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. airfast, beekit, beestack, coldfire+, corenet, flexis, magniv, mxc, platform in a package, qoriq qonverge, quicc engine, ready play, safeassure, smartmos , turbolink, vybrid, and xtrinsic are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? 2012 freescale semiconductor, inc.

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